With the recent trend toward ever higher frequencies of signals, package board materials are required to be of low dielectric constant and low dielectric loss tangent. Therefore, the current mainstream of package board material is shifting from ceramics to resins.
More recently, since higher wiring densities are also required and the printed circuit board known as the multilayer buildup printed circuit board comprising a plurality of circuit layers is getting a more dominant position.
The multilayer printed circuit board called the multilayer buildup printed circuit board is generally manufactured by the semi-additive process in which a conductor circuit of copper or the like and an interlayer resin insulating layer are built up successively and alternately on the so-called core board which is a resin sheet reinforced with glass cloth or the like and measuring about 0.6 to 1.5 mm in thickness. In such a multilayer printed circuit board, the electrical interconnection of the conductor circuits isolated by interlayer resin insulating layers is obtained with via holes.
Heretofore, buildup multilayer printed circuit boards have been manufactured by the technologies disclosed in Japanese Kokai Publication Hei-9-130050, Japanese Kokoku Publication H4-55555 and Japanese Kokai Publication He-7-235743.
More particularly, through holes are formed a copper-clad laminate carrying copper foil thereon and, then, subjected to electroless copper plating to provide plated-through holes therein. The surface of the substrate board is then etched imagewise, to provide a conductor circuit thereon. This conductor circuit is provided with a roughened surface by electroless plating or etching on this conductor circuit and an interlayer resin insulating layer comprising epoxy resin, acrylic resin, fluororesin or a mixed resin thereof is constructed on said roughened surface. Then, via holes are formed by light exposure and development or laser processing and the resin is UV-cured and postcured to provide the objective interlayer resin insulating layer.
This interlayer resin insulating layer is also subjected to surface roughening treatment and, then, a thin electroless plated metal layer is formed thereon. Thereafter, a plating resist is disposed on the electroless plated metal layer and a thick electroplated layer is then formed. The plating resist is then stripped off and etching is performed to provide a conductor circuit connected to the lower-layer conductor circuit by way of via holes.
The above sequence of steps is repeated and, then, as the outermost layer, a solder resist layer for protection of the conductor circuit is formed. This solder resist layer is formed with openings and the conductor layer in the areas corresponding to the openings is plated to provide pads. Solder vamps are then formed to complete the manufacture of a buildup multilayer printed circuit board.
When the surfaces of the interlayer resin insulating layer and conductor circuit are roughened so as to insure good adhesion as in the above conventional manufacturing process, the carrying of high frequency signals results in that the signals selectively travel in the surface of the roughed layer of the conductor circuit owing to a skin effect and the problem of signal conduction noise tends to occur on account of the surface irregularities.
Furthermore, the epoxy acrylate resin which is generally used for inter-level resin isolating layer is low in fracture toughness and circuit boards using this resin tends to undergo cracking across the interface between the conductor circuit and the resin insulating layer under the conditions of the heat cycle test.
In addition, the multilayer printed circuit boards thus fabricated using a mixture of epoxy resin, acrylic resin, etc. has a high dielectric constant of more than 3.5 in the GHz band, therefore, when an LSI chip or the like employing high-frequency signals of a GHz band is mounted, the signal delay and signal error due to the high dielectric constant of the interlayer resin insulating layer are sometimes encountered.
Moreover, when the multilayer printed circuit board is one employing fluororesin as the material for interlayer resin insulating layers, while the fluororesin has low dielectric constant, low hygroscopicity and high in fracture toughness, the substrate board must be heated to a temperature close to 350° C. in the pressure-laminating stage for construction of an interlayer resin insulating layer but any printed circuit board which has experienced such a high-temperature environment tends to undergo early aging.
In the process for manufacturing a multilayer printed circuit board as disclosed in Japanese Kokai Publication Hei-6-283860, a roughened layer comprising acicular crystals of Cu—Ni—P alloy is first formed by electroless plating over the surface of an internal conductor circuit on a core board and then an interlayer resin insulating layer is built on this roughened layer. This interlayer resin insulating layer is then formed with openings for via holes. The substrate board is then plated to fill said openings with a conductor and, at the same time, provide a caplayer conductor circuit on said interlayer resin insulating layer. This serial construction of a conductor circuit and an interlayer resin insulating layer is repeated to provide a multilayer printed circuit board.
According to the above production technology for a multilayer buildup printed circuit board as disclosed in Japanese Kokai Publication Hei-6-283860, a necessary adhesion between the conductor circuit and the interlayer resin insulating layer superposed thereon is insured by provision of a Cu—Ni—P acicular alloy layer on the conductor circuit.
However, the manufacture of a circuit board generally involves cleaning of the substrate board with an acid and a chromic acid treatment for the surface of the interlayer resin insulating layer provided with openings for via hole and, when such a roughened layer composed of Cu—Ni—P acicular alloy exists on the conductor circuit, a local cell reaction with the copper constituting the conductor circuit may take place to dissolve the conductor circuit.
To prevent such dissolution of the conductor circuit, Japanese Kokai Publication Hei-9-130050 discloses a technology for inhibiting the local cell reaction by covering the roughened layer composed of Cu—Ni—P acicular alloy with a metal such as Sn.
However, multilayer printed circuit boards at the product level are not uniform in the density of conductor circuits so that it is difficult to completely cover the rough Cu—Ni—P acicular alloy layer with a Sn layer and thereby prevent dissolution of the conductor circuit. Furthermore, when the plating of the conductor circuit with Cu—Ni—P acicular alloy is repeated and the plating bath is degraded, the problem occurred that the plating metal can hardly be deposited effectively on the conductor circuit.
Furthermore, as mentioned above, when the roughening treatment is applied to the conductor circuit, signals are carried selectively by the superficial portion of the conductor circuit so that the signal delay is sometimes induced by the surface irregularities. This trouble is particularly pronounced when the substrate is a resin board which is lower in dielectric constant and dielectric loss tangent than a ceramic board.
Furthermore, a resin board is poor in heat radiation factor as compared with a metal or ceramic board and, hence, liable to accumulate heat, with the result that the ion diffusion rate of the copper constituting the conductor circuit is high and this ion migration tends to destroy the layer to layer insulation.
Therefore, Japanese Kokai Publication Hei-7-45948 and Japanese Kokai Publication Hei-7-94865 disclose the technology which comprises spin-coating one side of a ceramic or metal substrate with a resin, forming a layer of a metal (e.g. chromium, nickel or titanium) having good adhesion to the conductor circuit on the resin coat by sputtering, and then constructing a conductor circuit thereon.
However, this is a technology for building up conductor circuits and interlayer resin insulating layers chiefly on one side of a substrate board and unlike the case of using a ceramic board or a metal road, the resin substrate board cannot inhibit shrinkage and expansion of the interlayer resin insulating layer to occur warps and cracks which are sometimes induced across the interface between the interlayer resin insulating layer and the conductor circuit.
Furthermore, when an attempt is actually made to construct a conductor circuit by using this technique, there is sometimes encountered the trouble that the conductor circuit peels from the metal layer composed of, for example, chromium, nickel or titanium.
The cause of this trouble is as follows. Thus, when a metal layer is formed on the surface of a resin insulating layer by a physical vapor deposition technique, the metal layer exposed to a high deposition temperature is oxidized on the surface so that when a conductor circuit is formed directly on the oxidized surface, the interposition of the oxide layer between the metal layer and the conductor circuit weakens the adhesion so that the conductor circuit tends to peel off. Moreover, even if the metal layer is formed by a chemical vapor deposition technique or by plating, said surface oxidation occurs when the substrate board is allowed to sit in the air, so that the conductor circuit tends to peel off.
The use of a metal forming a passivation layer, such as Ni or Al, in the construction of said metal layer is disadvantageous in that etching with a rather easily manageable acid such as hydrochloric acid or sulfuric acid cannot proceed smoothly because the oxide once formed in the course of etching is not readily decomposed by the above-mentioned acid.
Furthermore, when an oxide film has been formed on the surface of such a metal layer, it is no longer easy to remove it by etching.
In addition, those metals are soluble in strong acid such as concentrated nitric acid and aqua regia and, therefore, can be etched with an etching solution based on concentrated nitric acid or a cyanide or fluoride solution but because these acids are toxic and violent substances not easy to handle, the process control is difficult and the work environment tends to be adversely affected.
There also is a technique for preventing the stripping of the interlayer resin insulating layer from the underlying conductor circuit and via holes by a roughening procedure which comprises performing copper electroplating to form a thick Cu film, then performing electroless nickel plating to form a thin nickel film on said thick Cu film and further superimposing a roughened layer composed of Cu—Ni—P alloy.
However, if, in the conventional manufacturing process for a multilayer printed circuit board, an electroless plated nickel film is formed on an electroplated film and, then, a roughened layer of Cu—Ni—P alloy is superimposed, the adhesion between the plated nickel film and a roughened layer of Cu—Ni—P alloy, which is usually high in adhesion, will be unexpectedly low so that the roughened layer of Cu—Ni—P alloy tends to be exfoliated from the plated nickel layer.
There also is the problem that, in the step of plating the conductor circuit with Cu—Ni—P alloy, the plating bath is progressively degraded because of repeated use thereof so that the plating metal will not be deposited neatly on the surface of the conductor circuit.
Moreover, in order to form a cover metal layer, e.g. an Sn layer, in the above process for manufacting a multilayer printed circuit board, the conductor circuit having a roughened surface must be electroless plated but this introduces complexity to the production process and leads to increased costs of production.
Moreover, when via holes are formed on such a conductor circuit having a cover metal layer, e.g. an Sn layer, a delamination trouble may take place in the areas of contact between the via holes and the underlying conductor circuit under the conditions of heating or the heat cycle test, thus reducing the connection reliability of the via holes.